The present invention relates to a semiconductor device including a variable resistor element.
“A variable resistor element,” a resistance value of which is variable by application of a voltage or a current thereto, is well known. A memory using the variable resistor element as a memory element is called “a variable resistance type memory”. ReRAM (Resistance Random Access Memory) can be cited as one example of the variable resistance type memories.
FIG. 1 shows a configuration of a memory cell array of ReRAM described in Japanese Unexamined Patent Application Publication No. 2010-257506. As shown in FIG. 1, a plurality of memory cells MCs are disposed in array. The memory cells MCs each are provided with one variable resistor element R cell, and one access transistor (select transistor) AT. The variable resistor element R cell has one end coupled to a plate line PL and the other end coupled to either one of the source/the drain of the access transistor AT. The other of either of the source/the drain of the access transistor AT is coupled to one of bit lines BLs while a gate of the access transistor AT is coupled to one of word lines (access lines) WLs.
FIG. 2 is a sectional view showing a structure of the Memory cell MC shown in FIG. 1. The access transistor AT is formed over a semiconductor substrate 100. Meanwhile, the variable resistor element R cell is formed in an interconnection layer above the semiconductor substrate 100. More specifically, the variable resistor element R cell is made up of a lower electrode 101, an upper electrode (the plate line PL, and a conductor film 103), and an insulator film 102 sandwiched between the lower electrode 101 and the upper electrode. Further, a via construction (104, 105) used for electrical coupling to a diffusion layer of the source/the drain of the access transistor AT over the semiconductor substrate 100 is formed directly underneath the lower electrode 101. That is, the variable resistor element R cell and the access transistor AT, incorporated in the same memory cell MC, are formed so as to be vertically separated from each other, being directly coupled to each other with the via construction (104, 105) interposed therebetween.
The following is well known as the technology related to the variable resistor element.
In Japanese Unexamined Patent Application Publication No. 2010-225868, there is disclosed a nonvolatile memory where variable resistance memory cells are disposed in a matrix configuration. The variable resistance memory cell is formed by stacking a diode material and a variable resistance material one another.
In Japanese Unexamined Patent Application Publication No. 2006-279042, there is disclosed a resistance memory cell. The resistance memory cell incorporates a first electrode plug that is vertically extended, a resistance memory element pattern that is horizontally disposed to cover the upper surface of the first electrode with the minimum width of a part thereof, covering the first electrode, being larger than the diameter of the first electrode plug, and a second electrode disposed over the resistance memory element pattern.
In Japanese Unexamined Patent Application Publication No. 2005-032401, there is disclosed a method for inhibiting occurrence of disturbance. The variable resistor element has one end coupled to a word line and the other end coupled to a bit line. A first word line voltage is applied to a select word line while a second word line voltage is applied to an unselect word line. A first bit line voltage is applied to a select bit line while a second bit line voltage is an unselect bit line. A voltage difference between the first word line voltage and the first bit line voltage is not less than a first voltage difference causing a change in resistance value of the variable resistor element. A voltage difference between the first word line voltage and the second bit line voltage, a voltage difference between the second word line voltage and the first bit line voltage, and a voltage difference between the second word line voltage and the second bit line voltage are each not higher than a second voltage difference causing no change in the resistance value of the variable resistor element.
In. Japanese Unexamined Patent Application Publication No. 2010-282673, there is disclosed a nonvolatile semiconductor memory provided with a three-dimensional memory cell array.